Phase-locked loops (PLLs) are used in data communications and telecommunications applications to lock onto the frequency and phase of a signal. In particular, PLLs are often used in clock and data recovery (CDR) applications. A typical PLL includes a phase detector, a charge pump, a loop filter, and a voltage controlled oscillator (VCO) that produces a VCO signal. One performance characteristic of a PLL is the 3 decibel (dB) frequency bandwidth. The 3 dB frequency bandwidth is a measure of the frequency bandwidth within which the PLL is able to track frequency changes of the input signal. The 3 dB frequency bandwidth is usually measured directly by phase modulating the input signal and observing the amplitude of the resulting output signal. The frequency at which the ratio of the input signal phase to the output signal phase (θout/θin, commonly known as the closed loop transfer function), drops from unity to −3 dB identifies the 3 dB frequency bandwidth. This technique for measuring the 3 dB frequency bandwidth requires a data source with a phase modulated clock to provide the phase modulated input signal and an external spectrum analyzer to measure the amplitude of the phase modulated output signal. Although this technique works well, the phase modulated clock and external spectrum analyzer add complexity and cost to the 3-dB frequency measurement.
In view of the above, what is needed is a technique for measuring the 3 dB frequency bandwidth of a PLL that is easy to use and cost effective to implement.